FPGA可编程逻辑器件芯片XC6VSX315T-L1FFG1156I中文规格书

FPGA可编程逻辑器件芯片XC6VSX315T-L1FFG1156I中文规格书

Packaging Overview

Summary

This chapter covers the following topics:

•Introduction

•Device/Package Combinations and Maximum I/Os

•Pin Definitions

Introduction

This section describes the pinouts for Virtex®-5 devices in the 1.00mm pitch flip-chip fine-

pitch BGA packages.

Virtex-5 devices are offered exclusively in high performance flip-chip BGA packages that

are optimally designed for improved signal integrity and jitter. Package inductance is

minimized as a result of optimal placement and even distribution as well as an increased

number of Power and GND pins.

All of the devices supported in a particular package are pinout compatible and are listed in

the same table (one table per package). Pins that are not available for the smaller devices

are listed in the “No Connects” column of each table.

For Virtex-5Q devices, the EF package is offered. The only difference between an EF and an

FF package is that the discrete substrate capacitors on the EF package are coated with

epoxy. The coating is comprised of an undercoat epoxy that is dispensed under the

capacitors and an overcoat epoxy that is dispensed over the top of the capacitors. All other

package construction characteristics of the EF matches that of the FF package. The EF

package changes are noted in Chapter4, “Mechanical Drawings.”

Each device is split into eight or more I/O banks to allow for flexibility in the choice of I/O

standards (see UG190: Virtex-5 FPGA User Guide). Global pins, including JTAG,

configuration, and power/ground pins, are listed at the end of each table. Table1-7

provides definitions for all pin types.

For information on package electrical characteristics and how the characteristics are

measured, refer to UG112: Device Package User Guide found on the Xilinx website.

For the latest Virtex-5 FPGA pinout information, check the Xilinx website for any updates

to this document.

Virtex-5 FPGA Packaging and Pinout Specification

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