FPGA可编程逻辑器件芯片EP1S20F484C7中文规格书

FPGA可编程逻辑器件芯片EP1S20F484C7中文规格书

Stratix III Device Handbook, Volume 1Remote System Upgrade

f Stratix III devices contain the remote update feature. For more information about this

feature, refer to the Remote System Upgrades with Stratix III Devices in volume 1 of the Stratix III Device Handbook .

Power-On Reset Circuit

The POR circuit keeps the entire system in reset until the power supply voltage levels have stabilized on power-up. On power-up, the device does not release nSTATUS until V CCPT , V CCL , V CC , V CCPD , and V CCPGM are above the device’s POR trip point. On power down, brown-out occurs if V CC or V CCL ramps down below the POR trip point and V CC , V CCPD , or V CCPGM drops below the threshold voltage.

In Stratix III devices, a pin-selectable option (PORSEL) is provided that allows you to select a typical POR time setting of 12ms or 100ms. In both cases, you can extend the POR time by using an external component to assert the nSTATUS pin low .

V CCPGM Pins

Stratix III devices offer a new power supply, V CCPGM , for all the dedicated configuration pins and dual function pins. The configuration voltages supported are 1.8 V , 2.5 V , 3.0V , and 3.3V . Stratix III devices do not support the 1.5V configuration.

Use this pin to power all dedicated configuration inputs, dedicated configuration outputs, dedicated configuration bi-directional pins, and some of the dual functional pins that you use for configuration. With V CCPGM , configuration input buffers do not have to share power lines with the regular I/O buffer in Stratix III devices.

The operating voltage for the configuration input pin is independent of the I/O bank’s power supply V CCIO during the configuration. Therefore, no configuration voltage constraints on V CCIO are needed in Stratix III devices.

V CCPD Pins

Stratix III devices have a dedicated programming power supply, V CCPD , which must be connected to 3.3V/3.0V/2.5V to power the I/O pre-drivers, the JTAG input and output pins (TCK , TMS , TDI , TDO, and TRST ), and the design security circuitry. 1V CCPGM and V CCPD must ramp up from 0V to the desired voltage level within 100ms. If

these supplies are not ramped up within this specified time, your Stratix III device will not configure successfully. If your system does not allow ramp-up time of 100ms or less, you must hold nCONFIG low until all power supplies are stable.

f

For more information about the configuration pins power supply, refer to “Device Configuration Pins” on page 11–43

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