RocketIO GTX Transceiver User Guide UG198 (v3.0) October 30, 2009

GTX Transmitter (TX)

This chapter shows how to configure and use each of the functional blocks inside the GTX transmitter.

Transmitter Overview

Each GTX transceiver in the GTX_DUAL tile includes an independent transmitter, which consists of a PCS and a PMA. Figure 6-1 shows the functional blocks of the transmitter. Parallel data flows from the FPGA into the FPGA TX interface, through the PCS and PMA, and then out the TX driver as high-speed serial data. Refer to Appendix E, “Low Latency Design,” for latency information on this block diagram.

The key elements within the GTX transmitter are:1.“FPGA TX Interface,” page 120

2.“Configurable 8B/10B Encoder,” page 129

3.“TX Buffering, Phase Alignment, and TX Skew Reduction,” page 141

4.“TX Polarity Control,” page 147

5.“TX Gearbox,” page 134

6.“TX PRBS Generator,” page 148

7.“Parallel In to Serial Out,” page 149

8.“Configurable TX Driver,” page 150


“Receive Detect Support for PCI Express Operation,” page 153

10.“TX Out-of-Band/Beacon Signaling,” page 157

Figure 6-1:GTX TX Block Diagram



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