FPGA可编程逻辑器件芯片XC6VSX475T-2FF1759C中文规格书

FPGA可编程逻辑器件芯片XC6VSX475T-2FF1759C中文规格书

7 Series FPGAs Packaging UG475 (v1.18) July 16, 2019Pin Definitions

Table 1-12 lists the pin definitions used in 7series FPGAs packages.

Note:There are dedicated general purpose user I/O pins listed separately in Table 1-12. There are also multi-function pins where the pin names start with either IO_LXXY_ZZZ_# or IO_XX_ZZZ_#, where ZZZ represents one or more functions in addition to being general purpose user I/O. If not

used for their special function, these pins can be user I/O.

FPGA可编程逻辑器件芯片XC6VSX475T-2FF1759C中文规格书

user I/O after stage 2 configuration is complete.

Table 1-12:7Series FPGAs Pin Definitions

Pin Name Type Direction Description

User I/O Pins IO_LXXY_#IO_XX_#Dedicated Input/Output Most user I/O pins are capable of differential signaling and can be implemented as pairs. The top and bottom I/O pins are always single ended. Each user I/O is labeled IO_LXXY_#, where:

°

IO indicates a user I/O pin °L indicates a differential pair, with XX a unique pair in the bank and Y = [P|N] for the positive/negative sides of the differential pair

°

# indicates a bank number Configuration Pins

For more information, see the Configuration Pin Definitions table in UG470, 7Series FPGAs Configuration User Guide .

CCLK_0

Dedicated (1)Input/Output Configuration clock. Output in Master mode or input in Slave mode DONE_0

Dedicated (1)Bidirectional DONE indicates successful completion of configuration (active High)INIT_B_0

Dedicated (1)Bidirectional (open-drain)Indicates initialization of configuration memory (active Low)M0_0, M1_0, or M2_0

Dedicated (1)Input Configuration mode selection PROGRAM_B_0

Dedicated (1)Input Asynchronous reset to configuration logic (active Low)TCK_0

Dedicated (1)Input JTAG clock TDI_0

Dedicated (1)Input JTAG data input TDO_0

Dedicated (1)Output JTAG data output TMS_0Dedicated (1)Input JTAG mode select

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